1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method and, in particular, to a semiconductor device and its manufacturing method in which, in the process of forming a contact between an impurity concentration layer formed in a semiconductor substrate and a polysilicon layer formed over the impurity concentration layer and the process of forming a contact between a conductive layer formed over the semiconductor substrate and a polysilicon layer formed over the conductive layer, the polysilicon layer being vapor-phase grown by a selective epitaxial growth (SEG) method in their contact hole.
2. Description of the Related Art
A conventional semiconductor device and its method of manufacture using a selective epitaxial growth (SEG) method for selectively vapor-phase growing a silicon layer 5 only in a hole of a contact between an impurity diffusion layer formed in a semiconductor substrate and an overlying polysilicon layer and a contact between a conductive layer formed over the semiconductor substrate and an overlying polysilicon layer will be explained below with reference to FIG. 4.
FIGS. 4A to 4C are cross-sectional views showing the steps of forming a semiconductor device using the SEG method whereby a silicon layer is formed.
In the step of FIG. 4A, an N-type impurity diffusion region pattern is formed in a P-type silicon semiconductor substrate 1 with the use of a photoresist, not shown. That is, with the photoresist as a mask, an N-type ion, such as arsenic, is implanted into the semiconductor substrate 1. Then, a silicon oxide film 3 of, for example, 6000 .ANG. thick is deposited over the whole surface of the resultant structure by means of a chemical vapor deposition (CVD) method. A contact hole 4 is opened, by a reactive ion etching (RIE) method, in the silicon oxide film 3 so as to correspond to the N type impurity diffusion layer.
In the step of FIG. 4B, an epitaxial silicon layer 5 (hereinafter referred to as an SEG silicon layer) is selectively formed, by the SEG method, in the contact hole 4 at which time the SEG silicon layer 5 is of a single crystal type.
In the step shown in FIG. 4C, a polysilicon layer 6 is deposited over the whole surface of the resultant structure, for example, by means of the CVD method, followed by the formation of a predetermined pattern. By so doing, a semiconductor device is manufactured in which the SEG silicon layer 5 is formed between the N-type impurity diffusion layer 2 and the CVD polysilicon layer 6.
However, a native oxide film 7 is formed at an interface of the SEG silicon layer 5 in the contact hole and the CVD polysilicon layer, as shown in FIG. 4C. Since the SEG silicon layer 5 and CVD polysilicon layer 6 are formed by the different steps, a wafer needs to be transferred from an SEG furnace to a CVD furnace. At this time, these furnaces are opened, allowing O.sub.2 in the outer atmosphere to enter into the CVD furnace at the latter step and a thermal oxide film (hereinafter referred to a native oxide) is formed on the surface of the wafer through a reaction with O.sub.2 under the furnace heat. A native oxide film 7 is also formed on the upper surface portion of the SEG silicon film 5. Therefore, there is an increase in a contact resistance between the SEG silicon layer 5 and the CVD polysilicon layer 6.